Dnotitia Targets AI Retrieval Bottlenecks with New Vector Silicon

The company’s shift from FPGA-based testing to chip-level characterization marks a pivotal move toward commercial deployment. During preliminary evaluations, a four-card VDPU server achieved 5.77 times the vector-search throughput of a standard dual-socket CPU server. Beyond raw speed, the architecture significantly reduced host overhead in 4,096-dimensional multimodal workloads, cutting host CPU utilization by 92% and memory consumption by 73% during index building.

Se-Hyun Yang, Chief Technology Officer at Dnotitia, notes that agentic AI has shifted infrastructure bottlenecks from model compute toward retrieval processes. By providing a dedicated processing layer for these tasks, the VDPU allows GPUs to focus on model execution while reclaiming host CPU capacity for primary applications. The current FPGA platform supports industry-standard libraries including Milvus, FAISS, and hnswlib, ensuring compatibility with existing enterprise environments.

With chip characterization currently underway, the company is preparing for silicon-based evaluations scheduled for Q4 2026. Dnotitia is aiming for a tenfold performance increase over CPU-based servers once the final ASIC architecture is fully implemented. The firm is now deepening integration discussions with storage, memory, and database partners to embed the technology into broader AI infrastructure stacks.